2024-03-12

Verifier to ASIC team – 7714

Arbetsplats - "Stockholm"

Yrke - Affärskonsult, IT

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Om jobbet

Veritaz is a leading IT staffing solutions provider in Sweden, committed to advancing individual careers and aiding employers in securing the perfect talent fit. With a proven track record of successful partnerships with top companies, we have rapidly grown our presence in the USA, Europe, and Sweden as a dependable and trusted resource within the IT industry. Assignment Description: We are looking for a Senior Verifier to ASIC team to join our dynamic team What You Will Work On: Participate in new and existing ASIC projects within the telecom sector, focusing on IP design/verification and SubSys integration/verification. Collaborate in team environments to contribute to the verification process for ASIC projects. Engage in a mix of IP block verification and SubSys integration/verification tasks. Utilize UVM verification methodology and SystemVerilog for ASIC verification activities. Work with complex ASIC and/or large FPGA designs, including multi-clock domains. Implement RTL designs using Verilog, VHDL, and/or SystemVerilog. Communicate effectively in English, both verbally and in written form.

What You Bring: Minimum 3 years of experience in ASIC verification, with familiarity with UVM preferred. Proficiency in UVM verification methodology and SystemVerilog. Experience with complex ASIC and/or large FPGA designs. Prior experience in IP block verification. Knowledge of RTL design within Verilog, VHDL, and/or SystemVerilog. Strong communication skills in English.

Meritorious if You Have: Experience in test bench structuring and design. Leadership qualities demonstrated in previous roles. Knowledge of RTL design. Proficiency in scripting languages. Lab experience related to ASIC verification. Background in the telecommunications industry.